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? 2011 semtech corporation power management 1 SC5010 high e ciency 8-channel led driver with i 2 c interface and phase-shifted pwm dimming features vin range 4.5v to 27v, vout range up to 50v step-up (boost) controller excellent transient response programmable switching frequency linear current sinks 8 strings, up to 30ma/string current matching 1% current accuracy 1.5% pwm dimming string-by-string phase shifting input dimming frequency 100hz-30khz user selectable 9 or 10 bits dimming resolution optional synchronization to vsync/hsync s ignal 5-bit analog dimming optional external p-mosfet disconnect switch true load disconnect and inrush current limiting i 2 c interface fault status open/short led, uvlo, otp device control sync freq, pll setting protection features open/shorted led(s) and adjustable ovp over-temperature and uvlo shutdown protection 4 x 4(mm) 28-pin qfn package applications notebook pcs, umpc, lcd monitors, and tablet pcs ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? description the SC5010 is an 8-channel high-precision, high-e ciency step-up (boost) led driver for backlight applications. it fea- tures wide input voltage range (4.5v to 27v) , exible output configuration, wide analog and pwm dimming range, phase shifting and fading. it also features video signal syn- chronization (vsync), i 2 c interface, and numerous protec- tion features. an optional disconnect p-mosfet provides true load disconnection and inrush current limiting. the boost controller, with programmable switching fre- quency from 200khz to 2.2mhz, maximizes e ciency by dynamically minimizing the output voltage while maintain- ing led string current accuracy. it provides excellent line and load response with no external compensation compo- nents. each linear current sink is matched within 1% for superb lighting uniformity, and the accuracy of each string current is 1.5%. an external resistor adjusts the current from 10-30ma per string. it also features pwm dimming resolution of 9 or 10 bits (user selectable) over dimming frequency from 100hz to 20khz, synchronized to the sync signal or the boost oscillator. string-by-string phase shifting reduces the demand on the input/output capacitance, decreases emi, and improves dimming linearity. SC5010 is available in a low-pro le, thermally enhanced, 4 x 4 x 0.6(mm) qfn 28-pin package. uvlo agnd iset fset cpll scp drvp vin SC5010 r3 r6 flt c3 bg flt vcc pgnd r11 r7 c4 r10 r1 r2 c1 q2 c2 ovp io8 io1 r9 r8 v in =4.5 to 27v up to 30ma/ch io2 io3 io4 io5 io6 c5 io7 r5 pwmi pwmi sync sync sda scl for i 2 c en en l1 q1 r4 drvn cs d1 v out up to 50v v cc = 4.5 to 5.5v (optional) 2.2 h 4.7 f typical application circuit revision 1.0 www.datasheet.co.kr datasheet pdf - http://www..net/
SC5010 2 pin con guration marking information ordering information device package SC5010ultrt (1)(2) mlpq-ut-28 44 SC5010evb evaluation board notes: (1) available in tape and reel only. a reel contains 3,000 devices. (2) lead-free packaging only. device is weee and rohs compliant, and halogen-free. agnd 103 20 io2 21 io4 19 io1 22 pwmi 14 io5 18 io6 17 io7 16 io8 15 vin 28 ovp 23 cs 24 pgnd 25 26 drvp 27 vcc 1 en 2 uvlo 3 scp 4 bg 5 fset 6 agnd 7 iset 12 13 scl 10 sda 11 sync 9 cpll 8 drvn flt 5010 yyww xxxxx xxxxx mlpq-28; 4x4, ep1 ja = 30c/w nnnn = part number yyww = date code xxxxx = semtech lot no. xxxxx = semtech lot no. www.datasheet.co.kr datasheet pdf - http://www..net/
SC5010 3 exceeding the above speci cations may result in permanent damage to the devic e or device malfunction. operation outside of the parameters speci ed in the electrical characteristics section is not recommended. notes: (1) tested according to jedec standard jesd22-a114-b. (2) calculated from package in still air, mounted to 3 x 4.5 (in.), 4 layer fr4 pcb with thermal vias under the exposed pad pe r jesd51 standards. absolute maximum ratings vcc pin (v) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +6.0 vin, drvp, io1 to io8(v) . . . . . . . . . . . . . . . . . . . . -0.3 to +30 drvn, ovp, cs, en, uvlo, scp, bg, flt (v) . . . -0.3 to +6.0 fset, cpll, sync, scl, sda, iset, pwmi (v) . . -0.3 to +6.0 pgnd to agnd (v) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 esd protection level (1) (kv) . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5 recommended operating conditions ambient temperature range (c) . . . . . . . . -40 < t a < +85 vin (v) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5 to 27 io1 to io8 current per string (ma) . . . . . . . . . . . up to 30 thermal information thermal resistance, junction to ambient (2) (c/w) . . . . 30 maximum junction temperature (c) . . . . . . . . . . . . . . +150 storage temperature range (c) . . . . . . . . . . . . -65 to +150 peak ir re ow temperature (10s to 30s) (c) . . . . . . +260 unless noted otherwise, t a = 25c for typical, -40c < t a = t j < 85c for min and max. v cc = 5v, r iset = 64.9 k, r fset = 100 k , v in = 12v. parameter symbol conditions min typ max units input supply v cc supply voltage v cc 4.5 5.5 v v cc under-voltage lockout threshold v cc-uvlo(th) v cc voltage rising 4.0 4.2 4.4 v v cc under-voltage lockout hysteresis v cc-uvlo(hys) v cc voltage falling 180 mv v cc quiescent supply current i cc(q) en = 5v, switching, no load 2 ma v cc supply current in shutdown i cc(sd) en = 0v 1 a v in supply current in shutdown i vin(sd) en = 0v, vin = 27v 1 a v uvlo under-voltage lockout threshold v uvlo(th) uvlo pin voltage rising 1.18 1.23 1.28 v i uvlo under-voltage lockout hysteresis i uvlo(hys) uvlo pin voltage falling 7 10 13 a v bg bandgap voltage v bg 1.20 1.23 1.26 v external fet gate drive drvn high level v drvn(h) 100ma from drvn to gnd v cc -0.5 v cc -0.2 v drvn low level v drvn(l) -100ma from drvn to v cc 0.2 0.5 v drvn on-resistance r drvn drvn high or low 2 5 ? drvn sink / source current i drvn drvn forced to 2.5v 1 a electrical characteristics www.datasheet.co.kr datasheet pdf - http://www..net/
SC5010 4 parameter symbol conditions min typ max units boost converter cs current limit threshold v cs(ilim) 0.36 0.40 0.44 v soft-start time (1) t ss from en to end of soft start 4.4 ms boost oscillator frequency f sw r fset = 100k 0.85 1 1.15 mhz boost oscillator frequency f osc r fset varies 0.2 2.2 mhz maximum duty cycle d max 85 90 % output disconnect gate drive drvp sink current i drvp(l) drvp = 12v 20 a drvp clamp voltage v clamp drvp oating, v clamp = v in - v drvp 57 8 v drvp pin leakage current i leak v drvp = 27v, v en = 0v 0.1 1 a control signals: en, pwmi, sync, sda, scl high voltage threshold v ih v cc = 4.5v to 5.5v 2.1 v low voltage threshold v il v cc = 4.5v to 5.5v 0.8 v sda output low v sda(l) -6ma from v cc to sda 0.3 v pin leakage current i leak v en = 0v, v vsync = v pwmi = v iset = v fset = v sda = v sdl = 5.0v -1 1 a pwm dimming input pwmi input dimming frequency f pwmi 100 30k hz sync input frequency f sync 30 100k hz pwmi input resolution 100hz < f pwmi < 10khz 10 bits 10khz < f pwmi < 20khz 9 bits over-voltage protection ovp trip threshold voltage v ovp(trig) ovp rising 1.1 1.2 1.3 v ovp hysteresis v ovp(hys) ovp falling 10 mv ovp leakage current i ovp(leak) ovp = 5v 0.1 1 a electrical characteristics (continued) www.datasheet.co.kr datasheet pdf - http://www..net/
SC5010 5 electrical characteristics (continued) parameter symbol conditions min typ max units current sink (io1 to io8) iox dimming minimum pulse width t pwm(min) f pwm(led) = 100hz - 30khz 300 ns iset pin voltage v iset 1.23 v regulation voltage v ion(reg) voltage of regulating string 0.6 v current sink disable threshold v ion(dis) checked at power-up 0.6 v current sink rise/fall time (1) t rise/fall r ising edge from 10% to 90% of i o(n) 25 ns led current accuracy i on(acc%) pwmi = 100%, t a = +25c 19.7 20 20.3 ma led current matching (2) i on(match) pwmi = 100%, t a = +25 c 1 % pwmi = 100%, t a = -40 c to +85 c 2 % i on o leakage current i on(leak) pwmi = 0v, en = 0v, v io1 ~ v io8 = 25v 0.1 1 a io switching frequency f pwm(io) fast_freq = 0 10 khz fast_freq = 1 (default setting) 20 phase delay time between io pins (io1 to io8) t pd fast_freq = 1 (default setting) t pd = (1/8)*(1/f pwm(io) ), 8 strings on 6.25 s pwm output resolution f pwm(io) = 10khz 10 bits f pwm(io) = 20khz 9 fault protection led short circuit protection threshold v ion(scp) r 4 and r 5 (3) 17xv scp 20xv scp 23xv scp v led open circuit protection threshold v io_ocp 0.2 v led short circuit fault delay t scp(delay) v ovp set to 1.5v, flt goes low 1 s flt pin leakage current i flt(leak) v en = 0v, v flt = 5.0v -1 1 a flt output low v flt(low) -5ma from flt to v cc 0.3 v over-temperature protection thermal shutdown temperature 150 c thermal shutdown hysteresis 10 c www.datasheet.co.kr datasheet pdf - http://www..net/
SC5010 6 parameter symbol conditions min typ max units i 2 c control interface: sda, scl timing speci cations scl clock frequency f scl 400 khz scl clock low period t low(scl) 1.3 s scl clock high period t high(scl) 0.6 s hold time start condition t hd(start) 0.6 s sda setup time t su(sda) 100 ns sda hold time t hd(sda) 0 0.9 s setup time stop condition t su(stop) 0.6 s bus free time between stop & start t bf 1.3 s notes: (1) ensured by design and characterization, not production tested (2) led current matching for 8 channels is defined as the largest of the two numbers, i.e., (max-avg)/avg and (avg-min)/avg; wh ere max is the maximum of led channel current, min is the minimum led channel current and avg is the average of the 8 led channel current. (3) refer to the detailed application circuit on page 21. electrical characteristics (continued) www.datasheet.co.kr datasheet pdf - http://www..net/
SC5010 7 typical characteristics backlight e ciency vs. input voltage backlight e ciency vs. input voltage backlight e ciency vs. led string current backlight e ciency vs. led string current pwm dimming linearity with phase shift v in (v) e ciency v in (v) e ciency led pwm dimming duty cycle (%) e ciency led pwm dimming duty cycle (%) 20ma/string 25ma/string 30ma/string 20ma/string 25ma/string 30ma/string 8p12s 8p10s 8p7s 25ma/string 8p10s 30ma/string 25ma/string 20ma/string 0 5 10 15 20 25 30 75 % 80 % 85 % 90 % 95 % 100 % 0 5 10 15 20 25 30 75 % 80 % 85 % 90 % 95 % 100 % 0 20 40 60 80 100 50 % 60 % 70 % 80 % 90 % 95 % 55 % 65 % 75 % 85 % e ciency 0 20 40 60 80 100 50 % 60 % 70 % 80 % 90 % 95 % 55 % 65 % 75 % 85 % v in = 6v v in = 12v 25ma/string, 8p10s, 20khz dimming v in = 6v v in = 12v v in = 24v 0.1 1 10 100 0.1 % 1 % 10 % 100 % led pwm dimming duty cycle (%) led string current change 0.1 1 10 100 0.1 % 1 % 10 % 100 % led pwm dimming duty cycle (%) led string current change pwm dimming linearity with phase shift 20ma/string, vin = 12.6v, 8p10s 20khz dimming 10khz dimming 1khz dimming www.datasheet.co.kr datasheet pdf - http://www..net/
SC5010 8 typical characteristics (continued) led string current matching vs. temperature led string current vs. r iset switching frequency vs. r fset v bg vs. temperature led string current change vs. analog dimming control register (idac) value led string current matching vs. analog dimming control register (idac) value led string current matching (%) idac register value (in decimal format) led string current change r fset (k ?? boost switching frequency (khz) led string current (a) r iset (k ?? -40 -20 0 20 40 60 80 100 0 0.4 % 0.8 % 1.2 % 1.6 % temperature (c) led string current matching 40 50 60 70 80 90 100 110 120 130 0.005 0.010 0.015 0.020 0.025 0.030 2400 2000 1600 1200 800 400 0 150 300 450 600 1.2300 1.2305 1.2310 1.2315 1.2320 -40 -20 0 20 40 60 80 100 temperature (c) v bg (v) 10 % 0 20 % 30 % 40 % 50 % 60 % 70 % 80 % 90 % 100 % 4 8 12 16 20 24 28 32 idac register value (in decimal format) 0 4 8 12 16 20 24 28 32 0.4 0.8 1.2 1.6 2.0 2.4 -40 c +85 c 0 c 25 c 0.035 20ma/string when idac = 31 (in decimal format) www.datasheet.co.kr datasheet pdf - http://www..net/
SC5010 9 typical characteristics (continued) led current fade in/out (logarithmic) led current fade in/out (linear) line transient response led open circuit protection load transient response time (100s/div) v_pwmi 5v/div. pwmi (10khz) = 2% to 98%, v in = 10.6v, 20ma/string x 6 fading disabled v o (ac coupled) 100mv/div. i o_led (total) 50ma/div. load transient response time (100s/div) v_pwmi 5v/div. v o (ac coupled) 100mv/div. i o_led (total) 50ma/div. 100% dimming, 30ma/string x 8 v in 10v/div. v lx 50v/div. i o_led (total) 200ma/div. i l 2a/div. time (2s/div) 8v 20v flt 5v/div. v en 5v/div. i o_led (total) 200ma/div. v out 20v/div. starting with one led string open-circuit time (20ms/div) time (40ms/div) pwmi 5v/div. v io1 5v/div. i o_led (total) 100ma/div. v out 20v/div. time (40ms/div) pwmi 5v/div. v io1 5v/div. i o_led (total) 100ma/div. v out 20v/div. pwmi (10khz) = 98% to 2%, v in = 10.6v, 20ma/string x 6 fading disabled www.datasheet.co.kr datasheet pdf - http://www..net/
SC5010 10 typical characteristics (continued) led dimming without phase shift led dimming with phase shift time (2ms/div) time (2ms/div) v io2 10v/div. i o_led (total) 100ma/div. i in 500ma/div. v io1 10v/div. v io2 10v/div. i o_led (total) 100ma/div. i in 500ma/div. v io1 10v/div. led dimming without phase shift led dimming with phase shift time (2ms/div) time (2ms/div) v io2 10v/div. i o_led (total) 100ma/div. i in 500ma/div. v io1 10v/div. v io2 10v/div. i o_led (total) 100ma/div. i in 500ma/div. v io1 10v/div. analog dimming transient via i 2 c analog dimming transient via i 2 c time (40s/div) v lx 20v/div. i o_led (total) 100ma/div. v out 2v/div. v sda 5v/div. 10% dimming @ 200hz, v in = 6v, output = 8p10s, 25ma/string 10% dimming @ 200hz, v in = 6v, output = 8p10s, 25ma/string 35% dimming @ 200hz, v in = 6v, output = 8p10s, 25ma/string 35% dimming @ 200hz, v in = 6v, output = 8p10s, 25ma/string 25ma/string to 10ma/string 10ma/string to 25ma/string time (40s/div) v lx 20v/div. i o_led (total) 100ma/div. v out 2v/div. v sda 5v/div. www.datasheet.co.kr datasheet pdf - http://www..net/
SC5010 11 typical characteristics (continued) synchronization of the led dimming to an external hsync input time (10s/div) time (400ns/div) v io1 5v/div. v hsync 5v/div. v lx 20v/div. v io2 5v/div. v io1 5v/div. v hsync 5v/div. led string current accuracy vs. temperature hsync = 48khz delay between hsync rising edge and turn- on of led string 1 -40 -20 0 20 40 60 80 100 19.50 temperature (c) led string current accuracy (ma) 19.75 20.00 20.25 20.50 20.75 21.00 20ma/string (nominal) vin start up time (20ms/div) v lx 20v/div. i o_led (total) 100ma/div. v out 20v/div. v in 5v/div. output = 8p10s, 25ma/string www.datasheet.co.kr datasheet pdf - http://www..net/
SC5010 12 pin descriptions pin # pin name pin function 1vcc input bias voltage supply for the ic accepts 4.5-5.5v inputs. add a 1f or larger ceramic bypass capacitor from this pin to ground. 2en logic high enable pin pull logic high to enable the device or pull low to disable and maintain low shutdown current. 3 uvlo input under-voltage lockout pin device is disabled when this pin is less than 1.23v (nominal). add a resistor divider from this pin to the input voltage and agnd, respectively. 4 scp short circuit led protection programming pin. shorted led protection disables the individual channel when the current sink voltage exceeds the programmed voltage threshold. adding resistor divider from this pin to bg and agnd programs the shorted-led protection up to 20x the v scp voltage. pulling the pin high to vcc disables the scp feature on all channels. 5 bg 1.23v bandgap output pin connect a 1f ceramic bypass capacitor from this pin to ground. 6 fset step-up (boost) frequency set pin connect a resistor from this pin to ground to set the frequency from 200khz to 2.2mhz. 7 agnd analog ground pin tie this pin to analog (quiet) ground isolated from the step-up (boost) converter switching current path. 8 cpll compensation for the internal pll connect a compensation resistor and capacitor from this pin to ground. this pin can be left oating if not used. 9sync sync input pin feeding the sync signal (30hz - 100khz) to this input results in internal pll being synchronized to the sync signal. this pin can be left oating if not used. 10 scl i 2 c serial clock input this pin must be connected to ground if not used. 11 sda i 2 c serial data input this pin must be connected to ground if not used. 12 iset led current programming pin connect an external resistor to ground to program the current in the led strings. for more details please refer to led string peak current programming on page 15. 13 flt logic low fault status pin open-drain output is latched low when fault condition is detected: open/short led, shorted string, ovp or otp. fault status can be reset by removing fault condition(s) and toggling the en, vcc or uvlo pins. this pin can be left oating if not used. 14 pwmi pwm dimming control input 15 io8 regulated current sink led channel 8 connect this pin to the cathode of the bottom led in string 8. connect pin to ground to disable this led string. 16 io7 regulated current sink led channel 7 connect this pin to the cathode of the bottom led in string 7. connect pin to ground to disable this led string. 17 io6 regulated current sink led channel 6 connect this pin to the cathode of the bottom led in string 6. connect pin to ground to disable this led string. 18 io5 regulated current sink led channel 5 connect this pin to the cathode of the bottom led in string 5. connect pin to ground to disable this led string. 19 io4 regulated current sink led channel 4 connect this pin to the cathode of the bottom led in string 4. connect pin to ground to disable this led string. www.datasheet.co.kr datasheet pdf - http://www..net/
SC5010 13 pin descriptions (continued) pin # pin name pin function 20 io3 regulated current sink led channel 3 connect this pin to the cathode of the bottom led in string 3. connect pin to ground to disable this led string. 21 io2 regulated current sink led channel 2 connect this pin to the cathode of the bottom led in string 2. connect pin to ground to disable this led string. 22 io1 regulated current sink led channel 1 connect this pin to the cathode of the bottom led in string 1. connect pin to ground to disable this led string. 23 ovp over-voltage feedback pin over-voltage activated when pin exceeds 1.2v. use a resistor divider tied to the output and gnd to set the ovp level. 24 cs step-up (boost) switch current sense pin connect a resistor from this pin to ground for current sense - utilized in peak current mode control loop and over-current sense circuitry. 25 pgnd power ground tie this pin to the power ground plane close to input and output decoupling capacitors. 26 drvn gate drive for the external step-up (boost) n-channel mosfet. 27 drvp gate drive for the external p-channel mosfet disconnect switch. 28 vin connect to the input power supply accepts 4.5v - 27v input. usually add 4.7f or larger ceramic bypass capaci- tor from this pin to ground. pad - thermal pad for heat-sinking purposes it is also agnd and should be connected to ground plane for proper circuit operation. www.datasheet.co.kr datasheet pdf - http://www..net/
SC5010 14 block diagram duty cycle mux iset ea minimum voltage detection otp drvp drvn hs ls 8 io1 io2 io3 io4 io5 io6 ovp en pwm sync cpll vcc cp vco led open/short fault sda scl pwm dim adjust otp 8 fset i 2 c interface cs iset adjust 1/n pll i-ref adj led freq adjust i 2 c (pll range) pwm freq. adjust 18 5-bit dac vin uvlo boost o scillator vbg scp bg x20 sc_ref duty cycle extractor recycle generator i 2 c interface and led control logic control logic flt oc/sc detection sc_ref io7 io8 comp 10 5 8 osc clim ++ - pwm comp slope comp 10mhz (system clk) pgnd agnd 10 8 8 dc dc bg 22 21 20 19 18 17 16 15 7 25 12 13 10 11 14 28 1 9 8 5 6 4 2 3 27 23 8 24 ilim + - + - ovp + - www.datasheet.co.kr datasheet pdf - http://www..net/
SC5010 15 general description the SC5010 contains a high frequency, current-mode, internally compensated boost controller and eight con- stant current sinks for driving led strings. the led current for all strings is programmed by an external resistor and the boost converter operates to maintain minimal required output voltage for regulating the led current to the pro- grammed value. a typical backlight application uses 3 to 14 leds for each string, with current driven up to 30ma. the unique control loop of the SC5010 allows fast tran- sient response in dealing with line and load disturbances. the SC5010 operating with an external power mosfet regulates the boost converter output voltage based on instantaneous requirement of the eight string current sources. this provides power to the entire lighting subsys- tem with increased e ciency and reduced component count. it supports pwm dimming frequencies from 100hz to 30khz and the supply current is reduced to typical 2ma when all led strings are o . start-up when the en pin is pulled up high (>2.1v), the device is enabled and the uvlo and vcc pin voltages are checked. the vcc voltage has xed under-voltage rising and falling trip points. if the vcc pin is higher than 4.2v and uvlo pin voltage is greater than 1.23v, the SC5010 goes into a startup sequence. the uvlo pin voltage can be used to program the input power source voltage vin turn on threshold and its hysteresis (refer to the detailed application circuit on page 21) as shown by the following equations: v in_turnon [v] = 1.23 x (r 1 + r 2 ) / r 1 v in_hysteresis [v] = 10 -5 x r 2 [ ] in the next phase, the SC5010 checks each io pin to deter- mine if the respective led string is enabled. each io pin is pulled up with a 100a current source. if any io pin is con- nected to gnd, it will be detected as an unused string, and will be turned o . this unused string checking proce- dure takes 1ms (typical). after this the SC5010 enters into a soft-start sequence. the soft-start function helps to prevent excess inrush current through the input rail during startup. in the SC5010, the soft-start is implemented by slowly ramping up the reference voltage fed to the error ampli er. this closed loop start-up method allows the output voltage to ramp up without any overshoot. the duration of the soft-start in SC5010 is controlled by an internal timing circuit which is used during start-up and its based on the boost converter switching frequency. for example, with switching frequency at 1mhz, it is typical 8ms and it becomes typical 4ms when the switching frequency is 2mhz. if pwmi voltage goes low while the SC5010 is in soft start operation, the SC5010 switches to standby mode. under such mode, the external power mosfet and the led current sources will be turned o immediately. the inter- nal soft-start timer is turned o and the soft-start value is saved. when the pwmi voltage goes high again, the soft- start resumes from the previously saved value. each led current source (io1 to io8) tries to regulate the led current to its set point. the control loop will regulate the output voltage such that all the io pin voltages are at least typical 0.6v. shutdown when the en pin is pulled down below 0.8v, the device enters into shutdown mode. in this mode, all the internal circuitry is turned o and the supply current is less than 1a(max). in the scenario when the en pin voltage is high, but either v in or vcc voltage falls below their respective uvlo threshold, the SC5010 goes into a suspend mode. in this mode, all the internal circuitry except the reference and the oscillator are turned o . thermal shutdown (tsd) if the thermal shutdown temperature of 150c is reached, the boost converter and all io current sources are turned o . flt pin is forced low in this situation. as temperature falls below the tsd trip point by 10c, the SC5010 will restart following the startup sequence as described before. the flt pin is latched and will stay low, it is reset by cycling the en, vcc, or uvlo. applications information www.datasheet.co.kr datasheet pdf - http://www..net/
SC5010 16 applications information (continued) boost converter operation the SC5010 includes a boost controller with programma- ble switching frequency. it applies current-mode control method with integrated compensation loop. the clock (see block diagram) from the oscillator sets the latch and turns on the external power mosfet, which serves as the main power switch. the current flowing through this switch is sensed by the current sense resistor in series with the switch. the sensed switch current is summed with the slope-compensated ramp and fed into the mod- ulating input of the pwm comparator. when the modulat- ing ramp intersects the error ampli er output (comp), the latch is reset and the power mosfet is turned o . the sense resistor also sets the peak current limit of the power mosfet, i ocp using the following equation: i ocp [a] = 0.4 / r cs [ ] the current-mode control system contains two loops. for the inner current loop, the error ampli er (ea) output (comp) controls the peak inductor current. in the outer loop, the ea regulates the output voltage for driving the led strings. boost converter switching frequency selection the resistor between fset and gnd sets the boost con- verter switching frequency (200khz to 2.2mhz) using the following equation: f sw [khz] = 10 5 / r fset [k] higher switching frequency allows the use of low pro le height inductor for space-constrained and cost-sensitive applications. over-voltage protection (ovp) SC5010 features programmable output over-voltage pro- tection preventing damage to the ic and output capacitor in the event of led string open-circuit. the boost converter output voltage is sensed at the ovp pin through resistor voltage divider. the ovp trip threshold (refer to detailed application circuit on page 21) can be calculated using the following equation. output ovp trip voltage [v] = 1.2 x (r 11 + r 10 ) / r 10 when the ovp pin voltage exceeds 1.2v, the boost con- verter turns o and the flt pin is pulled low. when the ovp pin voltage falls below the ovp threshold (falling), the boost converter restarts and the flt pin is released. there is 10mv hysteresis between ovp pin threshold (falling) and ovp pin threshold (rising). this results in an output voltage hysteresis given by: output ovp hysteresis[mv] = 10 x (r 11 + r 10 ) / r 10 led current sink the SC5010 provides 8 current sinks and each can sink up to 30ma current. it incorporates led string short-circuit protection (trip level programmable and can be disabled as well), led string open-circuit protection. led string peak current programming led string peak current (at 100% dimming) can be set by selecting resistor r iset , connected between iset and gnd. the relationship between r iset resistance and single led string peak current is calculated using the following equation: i led [ma] = (1055 x 1.23) / r iset [k] the led string current can be programmed up to 30ma. unused strings the SC5010 may be operated with less than 8 strings. in this mode of operation, all unused io pins should be con- nected to ground. during startup, these unused strings are detected and disabled while other active strings work normally. led short-circuit protection (scp) SC5010 features a programmable led short protection. this allows the part to be customized based on the led v f mismatches between the led strings. if one or more leds are detected as short-circuited, the corresponding string will be latched o . the voltages on all io pins are monitored to check if any io pin exceeds the scp trip point (the io voltage for led string with faulty short-circuit led(s) will be higher than other normal io pin voltages). this led short- circuit protection (scp) trip level (see detailed application circuit on page 21) is given by the following equation. v scp_trip [v] = 20 x (1.23 x r 4 ) / (r 4 + r 5 ) www.datasheet.co.kr datasheet pdf - http://www..net/
SC5010 17 if any io pin voltage exceeds the trip voltage, the io current sink will be latched o and the flt will go low. this latch can be reset by cycling uvlo, vcc or en. other led strings are una ected and continue in normal operation. this protec- tion will be disabled if scp is tied to vcc. in many applications, led strings are connected to the io pins through a mechanical connector which cannot support an electrical connection at speci c times. this connection might cause noise on the io pins. if this noise is large enough, it may trigger false scp mode. in this condition, a ceramic decoupling capacitors (100pf ~ 8.2nf) between io pin to gnd can help prevent the SC5010 from entering the protec- tion mode by false trigger. this feature can be disabled by connecting scp pin to vcc pin. led open-circuit protection if any led string becomes open, the respective io pin voltage will be pulled to gnd. consequently, the internal comp node (output of error ampli er) is driven high, which causes the boost output voltage to increase. the output voltage will be eventually clamped to a voltage set by the ovp resistor divider. under this condition, the faulty string is latched o and the flt pin is pulled low. the boost voltage gets regulated to the voltage required to set all non-faulty io pins above 0.6v (typ). the remaining strings remain in normal operation. the flt and the fault-out led current sink latch-o can be reset by cycling uvlo, vcc or en. applications information (continued) led analog dimming control the led current in SC5010 can be dimmed via the 5-bit analog dimming register (register 0x02). the led current can be adjusted in 32 steps from 0ma to the maximum value, determined by the r iset resistor. SC5010 has a unique dac architecture which allows it to have excellent led current accuracy and string-to-string matching over the entire dac range. analog dimming method can be used in conjunction with pwm dimming to increase the dimming resolution. the fast loop response of SC5010 allows the led current to transition to a new value within 100s or so. please refer to the graphs in the typical characteristics section. led pwm dimming control the SC5010 supports 3 modes of pwm dimming for con- trolling the brightness of the leds. it provides exibility in setting the duty cycle and frequency of the led pwm signal. the pwm dimming mode is set through the device control register (register address: 0x01) dcr [1:0] bits. refer to table 1 for more details. mode 1 pwmi direct control the pwmi input needs to be held high for normal opera- tion. pwm dimming can be done by cycling the pwmi input at a given frequency where a low on the pwmi input turns o all io current sinks and a high turns on all io current sinks. the pwmi pin can be toggled by external circuitry to allow pwm dimming. in a typical application, table 1 led pwm dimming control methods pwm dim- ming mode register settings dcr[1:0] pwm input source led pwm output phase shift option pwm frequency pwm duty cycle pwmi direct control 00 pwmi pin input same as the pwmi input (range 100 hz to 30khz same as the pwmi input no pwmi indirect control (default option) 01 pwmi pin input set via the freq register (0x05) and fast_freq bit 10khz (max): fast_freq=0 20khz(max): fast_freq=1 same as the duty cycle of the pwmi input 10 bits @ 10khz output 9 bits @ 20khz output yes i 2 c control 11 i 2 c control set via the freq register (0x05) and fast_freq bit 10khz (max): fast_freq=0 20khz(max): fast_freq=1 set via the duty cycle control register (0x03, 0x04) 10 bits @ 10khz output 9 bits @ 20khz output yes www.datasheet.co.kr datasheet pdf - http://www..net/
SC5010 18 applications information (continued) a micro-controller sets a register or counter that varies the pulse width on a gpio pin. the SC5010 allows dimming over a wide frequency range (100hz-30khz) in order to allow compatibility with a wide range of devices. this includes the newest dimming strategies that avoid the audio band by using high frequency pwm dimming. in this manner, a wide range of illumination can be gener- ated while keeping the instantaneous led current at its peak value for high e ciency and color temperature. the SC5010 provides 1000:1 dimming range at 1khz pwm fre- quency. the led current sinks turn on /off very rapidly (<25ns, typical). this allows wide dimming ratio. an addi- tional advantage of pwm dimming comes to customers who prefer to avoid in-rush currents when lling the boost output capacitor. apply the pwmi signal to the device at 10% duty for a millisecond or two, and in-rush current is reduced. this dimming time will vary based on the number of leds and the size of the output capacitor. this can be easily determined during testing and programmed into the micro-controller rmware. mode 2 indirect control this is the default mode for led pwm dimming in SC5010. in this mode, the input signal applied on pwmi pin is passed through a duty cycle extractor block. the extractor mea- sures the duty cycle of the pwmi input and converts it to a 10-bit value. this value is then passed to the pwm genera- tor block as shown in the figure 1 below. the led pwm output frequency is set via the freq regis- ter (address 0x05) and the fast_freq bit. with fast_freq = 0, low dimming frequency option is selected and the pwm dimming frequency will be accord- ing to the following equation. 10khz ( max ) ] 1 ] 0 : 7 [ freq [ 1024 mhz 10 frequency dimming pwm u with fast_freq = 1, high dimming frequency option is selected and the pwm dimming frequency is shown by the following equation. 20khz(max) ] 1 ] 0 : 7 [ freq [ 512 mhz 10 frequency dimming pwm u the default option is fast_freq = 1. this gives 9-bit duty cycle resolution and up to 20khz dimming frequency range. the pwmi input is usually generated by the system graphics processor. this mode allows the user to set the softstart 1 i 2 c interface 1 0 int_duty bit d[9:0] bits 10 pwm generator freq bits 10 phase shifting (45o) fastfreq bit ph_shift bit 8 en 1 0 pwmi 8 int_pwm bit extracted duty cycle from pwmi input led frequency and phaseshifter block pwm_ps[8:1] all bits identical when phase shifting disabled 8 pw m [8:1] 10 duty cycle extractor pwmi input figure 1 led pwm dimming control www.datasheet.co.kr datasheet pdf - http://www..net/
SC5010 19 applications information (continued) pwm output dimming frequency independent of the pwmi input. if the pwmi signal has jitter, then SC5010 provides an option to lter it out. hysteresis is also provided by select- ing the wnd[1:0] bits in the dcr register (address 0x01). wnd[1:0] bits set the window comparator such that if a change in the duty cycle is detected which is smaller than the set window, then it is ignored. mode 3 i 2 c control in this mode (see figure 1), both the output led duty cycle and the dimming frequency are set via the internal regis- ters. pwmi pin should be connected to ground in this mode. in this mode, the led dimming duty cycle is set via the duty cycle registers (address 0x03, 0x04); and the dimming frequency is set via the freq register (address 0x05) and the fast_freq bit. phase-shifted pwm dimming the SC5010 provides an option for the phase shifted led pwm dimming. this option is available in both pwmi indi- rect control and i 2 c control. phase-shift option is set by the ph_shift bit in the dcr register. this option delays the turn-on of the led strings based on the number of the strings in operation. it is shown by the following equation. frequency dimming pwm led f operation in strings of number n , n f 1 t pwm pwm phase i phase-shift mode is disabled during soft-start, this allows the output to ramp up to the correct voltage in a con- trolled fashion. phase-shifting reduces the peak input current, decreases emi and improves the dimming linearity. the gures in the typical characteristic section shows the reduction in the input current with phase shift feature enabled compared to the non-phase shifted mode of operation. backlight fade-in and fade-out options the SC5010 features an option for fade-in and fade-out brightness control, which allows smooth transition from one brightness level to another. registers associated with this fading functions are shown in this section. fade option (register address 0x09) sets fade enable options, fade time, fade type. fade rate (register address 0x0a) sets fade step size option. fade option register allows user to select fading, choose between linear or logarithmic fading, and to set up the fading time. the default setting is fading enabled with logarithmic mode. the fading time is determined by the led pwm dimming frequency. an example for calculating the fading time is shown in this section assuming led pwm dimming frequency is 10khz, then the pwm dimming period is 100 s. fade setting is shown in the following table. duty cycle range step increment step interval 0 to 511 1 2 512 to 767 1 1 768 to 1024 2 1 10 bits are assigned for 1024 duty cycle settings. time required to go from 10% (102/1024) to 90% (922/1024) duty cycle can be calculated using the follow- ing equation. ms 115.1 t 1151 time total 1151 ) 768 922 ( 2 1 256 ) 102 511 ( 2 cycle total period) dimming (pwm s 100 t pwm pwm u u u optional synchronization to sync input the SC5010 provides an option to synchronize the led dimming to an external clock source connected to the sync pin. in certain applications, it may be bene cial to synchronize the led drive signal to the lcd screen refresh signals such as vsync or hsync. this helps reduce or eliminate some of the problems associated with using led backlights, such as ickering, shimmering, etc. the phase lock loop available on the SC5010 can be pro- grammed via i 2 c to synchronize the internal 10mhz oscil- 1. 2. www.datasheet.co.kr datasheet pdf - http://www..net/
SC5010 20 lator to the sync input. figures on page 11 show synchronization of SC5010 to a 48khz hsync signal applied on sync pin. the turn-on of the led string io1 (falling edge of v io1 ) is synchronized to the rising edge of the hsync input. the turn-on of rest of the strings will be delayed based on the phase shifting algorithm. another gure shows the delay (~500ns) between hsync rising edge and turn-on of the led string 1 (io1). input disconnect the SC5010 incorporates a high voltage (up to 27v) p- mosfet gate driver which can be used for controlling an table 2 fault protection descriptions type of fault user disable? fault criteria action on fault recovery device flt pin (latching / non-latching condition(s) flt pin input under-voltage at vin (uvlo) no v in < 1 + r 2 /r 1 ) x 1.23 (rising) no startup not active v uvlo > 1.23v (rising) high no v in < (1 + r 2 /r 1 ) 1.23v - i uvlo r 1 (falling) shutdown not active v uvlo > 1.23v (rising) high input under-volage at vcc (uvlo) no vcc < 4.2v (rising) no startup not active vcc > 4.2v (rising) high no vcc < 4.0v (falling) shutdown not active vcc > 4.2v (rising) high over-voltage protection (ovp) no v ovp > 1.2v (rising) regulate to ovp threshold: i o(n) = on low (non-latching) v ovp > 1.2v (falling) high on re- moval of fault condition over-current protection (ocp) no v cs > 0.4v limit q1 fet drain current < 0.4v/r3 (typ) high v cs > 0.4v high shorted led(s) yes, tie scp to vcc v io(n) > 20 x v scp device on: i o(n) = o other i o(all) = on low (latching) replace shorted led(s) and toggle en, vcc or uvlo high v io(all) > 20 x v scp device latch-o ; i o(all) = o low (latching) replace shorted led(s) and toggle en, vcc or uvlo high open led(s) no v io(n) < 0.1v and ovp event device on: i o(n) = o other i o(all) = on low (latching) replace open led(s) and toggle en, vcc or uvlo high v io(all) < 0.1v and ovp event device latch-o ; i o(all) = o low (latching) replace open led(s) and toggle en, vcc or uvlo high over-tempera- ture protection (otp) no tj > 150oc (typ) device o ; i o(all) = o low (latching) satisfy t hys > 10oc; device on; i o(all) = on; toggle en, vcc or uvlo high note: refer to the application circuit example on page 21. applications information (continued) www.datasheet.co.kr datasheet pdf - http://www..net/
SC5010 21 applications information (continued) external p-channel mosfet. the external p-channel mosfet provides load disconnection during shutdown or fault mode. it also provides input inrush current limiting during start-up. during shutdown, the drvp pin is pulled up to vin voltage via an internal 1m ? resistor. at startup, the boost converter is held o and the drvp pin is pulled low via an internal 20 a (typ) current source. when the drvp pin is pulled lower than the threshold voltage of the external p-channel mosfet, the input current starts charging up the output capacitor to the input voltage. after that, the boost converter enters into soft start mode. fault protection SC5010 provides fault detection for low supply voltage, led related faults, missing v sync input, boost converter over-voltage and thermal shutdown. the open drain output pin (flt) indicates a system fault. the nature of the fault can be read from the fault status resistor (register address: 0x00) via i 2 c interface. refer to table 2 for a description of the fault protection modes. other possible con gurations depending on different application requirement, the SC5010 can also be easily con gured to other topology such as sepic (single-ended primary-inductor converter) con guration as shown in figure 3. figure 2 detailed application circuit c5 2.7pf vin (5-27v) u1 s c5010 vcc 1 en 2 uvlo 3 scp 4 bg 5 fset 6 agnd 7 cpll 8 sync 9 scl 10 sda 11 iset 12 13 pwm 14 io8 15 io7 16 io6 17 io5 18 io4 19 io3 20 io2 21 io1 22 ovp 23 cs 24 thp pgnd 25 drvn 26 drvp 27 vin 28 dfls140 r4, 10k ? c4 100pf r3 c6 q1 si2318 q2 si7129 c2 sda r8 r15 c7 10nf c1 scl c3 l1 4.7 h r9 r1 pwmi r10 vcc (5v) r6 r2 agnd r11 sync vout 10 wleds per channel pad flt flt 2.2 f 10k ? pgnd 4.7 f 4.7 f x 2 1 f 30k ? 0.1 ? 287k ? 10k ? 64.9k ? r7, 110k ? 20k ? 10k ? r5, 10k ? 100k ? www.datasheet.co.kr datasheet pdf - http://www..net/
SC5010 22 applications information (continued) c5 vin (5-27v) u1 s c5010 vcc 1 en 2 uvlo 3 scp 4 bg 5 fset 6 agnd 7 cpll 8 sync 9 scl 10 sda 11 iset 12 13 pwm 14 io8 15 io7 16 io6 17 io5 18 io4 19 io3 20 io2 21 io1 22 ovp 23 cs 24 thp pgnd 25 drvn 26 drvp 27 vin 28 d1 r4 c4 r3 c6 q1 q2 c2 sda r8 r15 c7 c1 scl c3 l1 r9 r1 pwmi r10 vcc (5v) r6 r2 agnd r11 sync vout pad flt flt 2.2 f pgnd 1 f 0.1 ? r7 r5 c8 l2 figure 3 sepic con guration high output voltage con guration if high output voltage application is required, an addi- tional external cascode mosfet can be added on each io pin to meet such requirement, please refer to gure 4 for reference. in this case, the upper limit on the output voltage is mainly determined by the rating of the external mosfet, heat dissipation, etc. pcb layout considerations the placements of the power components outside the SC5010 should follow the layout guidelines of a general boost converter. the detailed application circuit is used as an example. capacitor (c2) should be placed as close as possible to the vcc and agnd to achieve the best performance. capacitor (c1) is the input power ltering capacitor for the boost, it needs to be tied to pgnd. the converter power train inductor (l1) is the boost converter input inductor. use wide and short traces connecting these components. the output rectifying diode (d1) uses a schottky diode for fast reverse recovery. transistor (q1) is the external switch. resistor (r9) is the switch current sensing resistor. to minimize switching noise for the boost converter, the output capacitor (c6) should be placed such that the loop formed by q1, d1, c6 and r9, is minimized. the output of the boost converter is used to power up the leds. use wide and short trace connecting pin drvn and the gate of q1. the gnds 1. 2. 3. 4. www.datasheet.co.kr datasheet pdf - http://www..net/
SC5010 23 applications information (continued) c5 vin (5-27v) u1 s c5010 vcc 1 en 2 uvlo 3 scp 4 bg 5 fset 6 agnd 7 cpll 8 sync 9 scl 10 sda 11 iset 12 13 pwm 14 io8 15 io7 16 io6 17 io5 18 io4 19 io3 20 io2 21 io1 22 ovp 23 cs 24 thp pgnd 25 drvn 26 drvp 27 vin 28 d1 r4 c4 r3 c6 q1 q2 c2 sda r8 r15 c7 10nf c1 scl c3 l1 r9 r1 pwmi r10 vcc (5v) r6 r2 agnd r11 sync vout pad flt flt 2.2 f 10k ? pgnd 4.7 f 1 f 30k ? 0.1 ? r7 20k ? 10k ? r5 100k ? vcc (5v) figure 4 cascode con guration (for high output voltage application) for r9 and c6 should be pgnd. these components should be close to the SC5010. resistor (r8) is the output current adjusting resistor for io1 through io8 and should return to agnd. place it next to the ic. resistor (r6) is the switching frequency adjusting resistor and should return to agnd. place it next to the ic. the decoupling capacitor (c3) for pin bg should return to agnd. place it next to the ic. resistors (r4, r5) form a divider to set the scp level, r4 should return to agnd. place it next to the ic. resistors (r2, r1) form a divider to set the uvlo level for v in . r1 should return to agnd. place it next to the ic. r11 and r10 form a divider to set the ovp level for 5. 6. 7. 8. 9. 10. vout, r10 should return to agnd. place it next to the ic. all the traces for components with agnd connection should avoid being routed close to the noisy areas. an exposed pad is located at the bottom of the SC5010 for heat dissipation. a copper area underneath the pad is used for better heat dissipation. on the bottom layer of the pcb another copper area, connected through vias to the top layer, is used for better thermal performance. the pad at the bottom of the SC5010 should be connected to agnd. agnd should be connected to pgnd at single point for better noise immunity. 11. 12. www.datasheet.co.kr datasheet pdf - http://www..net/
SC5010 24 components selection inductor selection the choice of the inductor a ects the converters steady state operation, transient response, and its loop stability. special attention needs to be paid to three speci cations of the inductor, its value, its dc resistance and saturation current. the inductors inductance value also determines the inductor ripple current. the boost converter will operate in either ccm (continuous conduction mode) or dcm (discontinuous conduction mode) depending on its operating conditions. the inductor dc current or input current can be calculated using the following equation. v i v i in out out in u u i in ? input current; i out ? output current; v out ? boost output voltage; v in ? input voltage; ? ef ciency of the boost converter. then the duty ratio under ccm is shown by the following equation. d out d in out v v v v v d v d ? forward conduction drop of output rectifying diode when the boost converter runs under dcm ( l < l boundary ), it takes the advantages of small inductance and quick transient response; where as if the boost converter works under ccm (l > l boundary ), normally the converter has higher e ciency. when selecting an inductor, another factor to consider is the peak-to-peak inductor current ripple, which is given by the following equation. l f d v ? i sw in l u u usually this peak-to-peak inductor current ripple can be chosen between 30% to 50% of the maximum input dc current. this gives the best compromise between the inductor size and converter e ciency. the peak inductor current can be calculated using the following equation. sw in in l-peak for most applications, an inductor with value of 2.2 h to 22 h should be acceptable, (refer to the typical application circuit on page 21). the inductor peak current must be less than its saturation rating. when the inductor current is close to the saturation level, its inductance can decrease 20% to 35% from the 0a value depending on the vendor speci cations. using a small value inductor forces the converter in dcm, in which case the inductor current ramps down to zero before the end of each switching cycle. it reduces the boost converters maximum output current and produces larger input voltage ripple. the dcr of the inductor plays a signi cant role for the total system e ciency and usually there is a trade-o between the dcr and size of the inductor. table 3 lists some recommended inductors and their vendors. table 3 ? recommended inductors inductor web site xfl4020, 2.2h ~ 4.7h www.coilcraft.com dr73, 4.7h ~ 22h; dr74, 4.7h ~ 22h www.cooperet.com ihlp-2525cz-01, 4.7h ~ 10h www.vishay.com ds84lc, 4.7h ~ 10h; d62lcb, 4.7h ~ 22h www.toko.co.jp output capacitor selection the next design task is targeting the proper amount of output ripple voltage due to the constant-current led loads. usually x5r or x7r ceramic capacitor is recom- mended. the ceramic capacitor minimum capacitance needed for a given ripple can be estimated using the fol- lowing equation. v ripple ? peak to peak output ripple. the ripple voltage should be less than 200mv (pk-pk) to ensure good led current sink regulation. for example, a typical application where 20ma/channel current is needed, the total output current for 8 channels will be www.datasheet.co.kr datasheet pdf - http://www..net/
SC5010 25 components selection (continued) 160ma, and 1x 10f or 2x 4.7f capacitors are recommended. during load transient, the output capacitor supplies or absorbs additional current before the inductor current reaches its steady state value. larger capacitance helps with the overshoot/undershoots during load transient and loop stability. recommended ceramic capacitor manufacturers are listed in table 4. table 4 recommended ceramic capacitor vendors vendor web site kemet www.kemet.com vishay www.vishay.com tdk www.tdk.com murata www.murata.com taiyo yuden www.t-yuden.com input capacitor selection x5r or x7r ceramic capacitor is recommended for input bypass capacitor. a 1f capacitor is su cient for the vcc input. bypass the vin input with a 4.7f or larger ceramic capacitor. output freewheeling diode selection schottky diodes are the ideal choice for SC5010 due to their low forward voltage drop and fast switching speed. table 5 shows several di erent schottky diodes that work properly with the SC5010. verify that the diode has a voltage rating greater than the maximum possible output voltage. the diode conducts current only when the power switch is turned o . the diode must be rated to handle the average output current. a diode rated for 1a average current will be su cient for most designs. table 5 recommended recti er diodes recti er diode vendor web site dfls140 www.diodes.com 1n5819hw www.diodes.com ss13/14/15/16, ss23/24/25/26 www.vishay.com external power mosfet selection the boost converter in SC5010 uses an external power mosfet to regulate the output voltage and output power to drive led loads. this boost switching structure has an advantage in that the SC5010 is not exposed to high voltage. only the external power mosfet, freewheeling diode and the inductor will be exposed to the output voltage. the external power mosfet should be selected with its voltage rating higher than the output voltage by minimum 30%. the current rating should be enough to handle the inductor peak current. low r ds (on) mosfets are preferred for achieving better e ciency. the gd (gate driver) on SC5010 provides 1a (peak) current driving capability which is suitable for most mosfets for high frequency operation. the average current required to drive the mosfet is given by the following equation. i gate = q g x f sw q g ? gate charge the r ds(on) and its rms current i s_rms of the power mosfet will generate the conduction loss using the following equation. p cond = i s_rms 2 x r ds(on) the mosfets switch loss can be calculated using the fol- lowing equation. p sw = ? x v in x i l_peak x f sw x (t on + t off ) where t on and t off are the mosfet?s on and off time and they can be estimated by the following equations. " 5 " ! 9 ! 4 w 7 j s o d w h d x j g u 2 1 " 5 ! 9 4 w 7 j s o d w h d x j g i 2 ) ) where t r , t f , q gd and v plateau can usually be found from data- sheet of the selected mosfet. r g is the resistance of the optional resistor connected in series on the gate of the mosfet. www.datasheet.co.kr datasheet pdf - http://www..net/
SC5010 26 components selection (continued) current sensing resistor selection the switch current is sensed via the current sensing resis- tor, r sns . the sensed voltage at this pin is used to set the peak switch current limit and also used for steady state regulation of the inductor current. the current limit com- parator has a trip voltage of 0.4v. r sns value is chosen to set the peak inductor and switch current using the follow- ing equation. i sw(peak) = 0.4/r sns the power dissipation in r sns can be calculated using the following equations. p r_sns = i rms 2 x r sns i rms = d x [i o /(1-d)] 2 i o = output dc current, d = duty cycle for the typical application circuit shown in the detailed application circuit (page 21), the power dissipation on the sensing resistor is shown by the following equations. assuming v in (min) = 5v and v out = 30v, thus d = 84%, p r_sns = [(0.12/0.16) 2 x 0.1] x 0.84 = 0.047(w) for this example, a 0.1 1% thick- lm chip resistor rated at 0.125w can be used. pll filter component selection the detailed application circuit on page 21 shows the optimal r/c lter components for the pll compensation. these are optimized for internal 1mhz switching fre- quency. please con tact semtech application group if a di erent switching frequency is selected. isolation mosfet selection the external p-channel mosfet provides load disconnec- tion during shutdown or fault condition. select a mosfet with low r ds(on) to limit the power loss. in order to implement inrush current limiting, a 10nf capacitor is connected between the gate and source ter- minal of the mosfet. if isolation is not required, then the drvp pin can be left oating. connect the vin directly to the inductor. www.datasheet.co.kr datasheet pdf - http://www..net/
SC5010 27 master responds with an 8 bit data byte consisting of the register address. the slave acknowledges and the master sends the repeated start condition [sr]. once again, the slave address is sent, followed by an eighth bit indicating a read. the slave responds with an acknowledge and the 8 bit data from the previously addressed register; the master then sends a non-acknowledge (nack). finally, the master terminates the transfer with the stop condition [p]. (3) stop separated reads stop-separated reads can also be used. this format allows a master to set up the register address pointer for a read and return to that slave at a later time to read the data. in this format the slave address followed by a write command are sent after a start [s] condition. the SC5010 then acknowledges it is being addressed, and the master responds with the 8-bit register address. the master sends a stop or restart condition and may then address another slave. after performing other tasks, the master can send a start or restart condition to the SC5010 with a read command. the device acknowledges this request and returns the data from the register location that had previ- ously been set up. serial interface the i 2 c general speci cation the SC5010 is a read-write slave-mode i 2 c device and complies with the philips i 2 c standard version 2.1, dated january 2000. the SC5010 has 11 user-accessible internal 8-bit registers. the i 2 c interface has been designed for program flexibility, supporting direct format for write operation. read operations are supported on both com- bined format and stop separated format. while there is no auto increment/decrement capability in the SC5010 i 2 c logic, a tight software loop can be designed to randomly access the next register independent of which register you begin accessing. the start and stop commands frame the data-packet and the repeat start condition is allowed if necessary. limitations to the i 2 c speci cations the SC5010 only recognizes seven bit addressing. this means that ten bit addressing and cbus communication are not compatible. the device can operate in either stan- dard mode (100kbit/s) or fast mode (400kbit/s). slave address assignment the seven bit slave address is 0101 111x. the eighth bit is the data direction bit. 0x5f is used for a write operation, and 0x5e is used for a read operation. supported formats the supported formats are described in the following subsections. (1) direct format write the simplest format for an i 2 c write is direct format. after the start condition [s], the slave address is sent, followed by an eighth bit indicating a write. the SC5010 i 2 c then acknowledges that it is being addressed, and the master responds with an 8 bit data byte consisting of the register address. the slave acknowledges and the master sends the appropriate 8 bit data byte. once again, the slave acknowledges and the master terminates the transfer with the stop condition [p]. (2) combined format read after the start condition [s], the slave address is sent, fol- lowed by an eighth bit indicating a write. the SC5010 i 2 c then acknowledges that it is being addressed, and the www.datasheet.co.kr datasheet pdf - http://www..net/
SC5010 28 i 2 c direct format write slave address register address data swa a ap s ? start condition w ? write = ?0? a ? acknowledge (sent by slave) p ? stop condition slave address ? 7-bit register address ? 8-bit data ? 8-bit i 2 c stop separated format read slave address register address slave address b data nack s w a a s/sr r a p p slave address s register address setup access master addresses other slaves register read access s ? start condition w ? write = ?0? r ? read = ?1? a ? acknowledge (sent by slave) nak ? non-acknowledge (sent by master) sr ? repeated start condition p ? stop condition slave address ? 7-bit register address ? 8-bit data ? 8-bit i 2 c combined format read slave address register address slave address data nack s wa a sr r a p s ? start condition w ? write = ?0? r ? read = ?1? a ? acknowledge (sent by slave) nak ? non-acknowledge (sent by master) sr ? repeated start condition p ? stop condition slave address ? 7-bit register address ? 8-bit data ? 8-bit www.datasheet.co.kr datasheet pdf - http://www..net/
SC5010 29 register map address name reset value bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x00 fault status 0x00 clf - led_ short led_ open sync_gd otp ovp fault 0x01 device control 0xb5 wnd1 wnd0 fast_ freq flt_en sync_en phase_ shift int_ duty int_pwm 0x02 analog dimming control 0x1f - - - idac4 idac3 idac2 idac1 idac0 0x03 dimming duty cycle control 1 0x00 ------d9d8 0x04 dimming duty cycle control 2 0x00 d7 d6 d5 d4 d3 d2 d1 d0 0x05 dimming fre- quency select 0x00 freq7 freq6 freq5 freq4 freq3 freq2 freq1 freq0 0x06 pll divider msb 0x00 ------ npll17 npll16 0x07 pll divider lsb2 0x00 npll15 npll14 npll13 npll12 npll11 npll10 npll9 npll8 0x08 pll divider lsb1 0x08 npll7 npll6 npll5 npll4 npll3 npll2 npll1 npll0 0x09 fade options 0x80 fade_en fade_ type --- step_ mul2 step_ mul1 step_ mul0 0x0a fade rate 0x00 - fade_ rate6 fade_ rate5 fade_ rate4 fade_ rate3 fade_ rate2 fade_ rate1 fade_ rate0 www.datasheet.co.kr datasheet pdf - http://www..net/
SC5010 30 de nition of registers and bits fault status register this register monitors various fault conditions. bit field de nition read / write description 0x00 [7] clf w clear latching ags bit. (set = 1 to clear otp, led_open, led_short and mask ovp for 32 to 64s) 0x00 [5] led_short r led string short circuit fault status 1 = one or more led strings short-circuit detected 0 = no led string short-circuit detected 0x00 [4] led_open r led string open circuit fault status 1 = one or more led strings open-circuit detected 0 = no led string open-circuit detected 0x00 [3] sync_gd r sync good signal indication 1 = sync input is detected 0 = no sync signal detected 0x00 [2] otp r thermal shutdown status 1 = otp (over-temperature protection) fault detected 0 = no otp (over-temperature protection) fault detected 0x00 [1] ovp r output over-voltage (ovp) fault 1 = output ovp fault detected 0 = no output ovp fault detected 0x00 [0] fault r or of all fault conditions 1 = any one, or some, or all of the fault conditions detected 0 = no fault detected www.datasheet.co.kr datasheet pdf - http://www..net/
SC5010 31 device control register this register provides di erent control features of the device. bit field de nition read / write description 0x01 [7:6] win[1:0] r/w a modi ed duty cycle sent into the pwmi pin replaces the existing saved duty cycle when its deviation from the saved duty is outside the window for two consecutive samples. 00 = 0 bits (no window) 01 = 1 bit window 10 = 2 bit window 11 = 3 bit window 0x01 [5] fast_freq r/w determines the led pwm dimming frequency selection: 0 = low pwm dimming frequency mode assuming 10-bit pwm duty cycle dimming, dividing the system clock 10mhz / (1024 x (freq+1)). 1 = high pwm dimming frequency mode assuming 9-bit pwm duty cycle dimming, dividing the system clock 10mhz / (512 x (freq+1)). 0x01 [4] flt_en r/w this bit enables fault checking: 0 = led_open and led_short faults are not checked. 1 = led_open and led_short faults are checked. 0x01 [3] sync_en r/w enables video signal synchronization with the pll: 0 = sync is disabled. 1 = pll tracks the sync input signal. 0x01 [2] ph_shift r/w enables string-by-string phase shifting. this is a dont care if int_pwm=0. 0 = phase shifting disabled. 1 = phase shifting is enabled 0x01 [1] int_duty r/w determines the duty cycle source. this is a dont care if int_pwm = 0. 0 = led duty cycle is set by the pwmi input 1 = led duty cycle is set by the 10-bit duty cycle control registers 0x01 [0] int_pwm r/w sets the led pwm dimming source. 0 = led pwm dimming driven directly from the pwmi input source (direct pwm dimming) 1 = led pwm dimming driven from an internal oscillator (required for phase-shifted pwm dimming); enables the pll. de nition of registers and bits (continued) www.datasheet.co.kr datasheet pdf - http://www..net/
SC5010 32 de nition of registers and bits (continued) analog dimming control register this register is used to program the led string current through the on-chip 5-bit dac. bit field de nition read / write description 0x02 [4:0] idac [4:0] r / w 5-bit analog dimming register the led string current can be evenly adjusted in 32 steps from 0ma to the maximum value determined by r iset . for example, if the maximum led string current set by r iset is 20ma/string, when idac[4:0] is set to be 0b00101, the led string current will be 20ma x 5/(2 5 -1) = 3.2ma/string. dimming duty cycle control register these two registers (0x03 and 0x04) combine together as a 10-bit register for controlling the pwm dimming duty cycle. bit field de nition read / write description 0x03 [1:0] 0x04 [7:0] d [9:0] r / w 10-bit pwm brightness setting this value is spread over registers: 0x03 (msb) and 0x04 (lsb). the led pwm dimming duty cycle can be evenly adjusted by the 10-bit register from 0 to 100% with d[9:0] value changes from 0 to 0x3f. dimming frequency select register this register is used to program the led pwm dimming frequency. bit field de nition read / write description 0x05 [7:0] freq [7:0] r / w this register sets the led dimming frequency. fast_freq = 1, then led dimming frequency is equal to 10mhz / (512 x (freq+1)) fast_freq = 0, then led dimming frequency is equal to 10mhz / (1024 x (freq+1)) pll control registers this register is used to set the pll divider value. bit field de nition read / write description 0x06 [1:0] 0x07 [7:0] 0x08 [7:0] npll [17:0] r / w these registers set the pll divider value the system clock is intended to run at 10mhz; this value divides the system clock down to a frequency comparable to the sync signals frequen- cy to allow pll synchronization. typical values are shown below. f in pll divider n register values fpll = (n+2) f in 60 hz 169,982 0x02 - 0x97 - 0xfe 10mhz 1 mhz 8 0x00 - 0x00 - 0x08 10mhz www.datasheet.co.kr datasheet pdf - http://www..net/
SC5010 33 fade options registers this register is used to select the fade in and fade out related features . bit field de nition read / write description 0x09 [7] fade_en r/w enables the fading feature. fade_en = 0: no fading; jumps directly to new pwm value. fade_en = 1: enables fading. 0x09 [6] fade_type r/w selects the fading type. fade_type = 0: logarithmic fading fade_type = 1: linear fading 0x09 [2:0] step_mul [2:0] r/w used to speed up fade time, when selected led pwm dimming frequency is low. de ne a 2 n multiplier of the fade amount. step_mul[2:0] = 000, n=0, multiplier = 1 step_mul[2:0] = 001, n=1, multiplier = 2 1 = 2 step_mul[2:0] = 010, n=2, multiplier = 2 2 = 4 step_mul[2:0] = 011, n=3, multiplier = 2 3 = 8 step_mul[2:0] = 100, n=4, multiplier = 2 4 = 16 step_mul[2:0] = 101~111, n=5, multiplier = 2 5 = 32 fade rate register this register is used to program the rate of the duty cycle change during the fade in and fade out operation. bit field de nition read / write description 0x0a [6:0] fade_rate [6:0] r / w de nes how often the duty is changed during a fade. fade rate = pwm output rate / (1 + fade_rate[6:0]) de nition of registers and bits (continued) www.datasheet.co.kr datasheet pdf - http://www..net/
SC5010 34 outline drawing mlpq-ut-28 4x4 www.datasheet.co.kr datasheet pdf - http://www..net/
SC5010 35 land pattern mlpq-ut-28 4x4 www.datasheet.co.kr datasheet pdf - http://www..net/
semtech corporation power management products division 200 flynn road, camarillo, ca 93012 phone: (805) 498-2111 fax: (805) 498-3804 www.semtech.com contact information SC5010 36 ? semtech 2011 all rights reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any conse- quence of its use. publication thereof does not convey nor imply any license under patent or other industrial or intellec- tual property rights. semtech assumes no responsibility or liability whatsoever for any failure or unexpected operation resulting from misuse, neglect improper installation, repair or improper handling or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the speci ed maximum ratings or operation outside the speci ed range. semtech products are not designed, intended, authorized or warranted to be suitable for use in life- support applications, devices or systems or other critical applications. inclusion of semtech products in such applications is understood to be undertaken solely at the customers own risk. should a customer purchase or use semtech products for any such unauthorized application, the customer shall indemnify and hold semtech and its o cers, employees, subsidiaries, a liates, and distributors harmless against all claims, costs damages and attorney fees which could arise. notice: all referenced brands, product names, service names and trademarks are the property of their respective owners. www.datasheet.co.kr datasheet pdf - http://www..net/

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